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100 ma, low quiescent current, cmos linear regulator adp120 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008C2009 analog devices, inc. all rights reserved. features input voltage range: 2.3 v to 5.5 v output voltage range: 1.2 v to 3.3 v output current: 100 ma low quiescent current i gnd = 11 a with zero load i gnd = 22 a with 100 ma load low shutdown current: <1 a low dropout voltage 60 mv @ 100 ma load high psrr 73 db @ 1 khz at v out = 1.2 v 70 db @ 10 khz at v out = 1.2 v low noise: 40 v rms at v out = 1.2 v no noise bypass capacitor required initial accuracy: 1% stable with small 1 f ceramic output capacitor current-limit and thermal overload protection logic controlled enable 5-lead tsot package 4-ball 0.4 mm pitch wlcsp applications mobile phones digital camera and audio devices portable and battery-powered equipment post regulation typical applications circuits nc = no connect vin gnd en 5 vout 4 nc + 1f v out = 1.8v 1 2 3 + 1f v in = 2.3v 07589-001 figure 1. adp120 tsot with fixed output voltage, 1.8 v vin vout en gnd + 1f v out = 1.8v + 1f v in = 2.3v 07589-002 figure 2. adp120 wlcsp with fixed output voltage, 1.8 v general description the adp120 is a low quiescent current, low dropout, linear regulator that operates from 2.3 v to 5.5 v and provides up to 100 ma of output current. the low 60 mv dropout voltage at 100 ma load improves efficiency and allows operation over a wide input voltage range. the low 22 a of quiescent current at full load makes the adp120 ideal for battery-operated portable equipment. the adp120 is available in output voltages ranging from 1.2 v to 3.3 v. the part is optimized for stable operation with small 1 f ceramic output capacitors. the adp120 delivers good transient performance with minimal board area. short-circuit protection and thermal overload protection circuits prevent damage in adverse conditions. the adp120 is available in a tiny 5-lead tsot and a 4-ball 0.4 mm pitch wlcsp and utilizes the smallest footprint solution for use in a variety of portable applications.
adp120 rev. b | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 typical applications circuits .......................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 recommended specifications: input and output capacitors ...................................................................................... 4 absolute maximum ratings ............................................................ 5 thermal data ................................................................................ 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configurations and function descriptions ............................6 typical performance characteristics ..............................................7 theory of operation ...................................................................... 11 applications information .............................................................. 12 capacitor selection .................................................................... 12 undervoltage lockout ............................................................... 13 enable feature ............................................................................ 13 current-limit and thermal overload protection ................. 14 thermal considerations ............................................................ 14 pcb layout considerations ...................................................... 17 outline dimensions ....................................................................... 18 ordering guide .......................................................................... 19 revision history 4/09rev. a to rev. b change to general description section ........................................ 1 changes to table 2 ............................................................................ 4 changes to figure 17 to figure 20 .................................................. 9 changes to figure 49 ...................................................................... 17 added figure 50 .............................................................................. 17 changes to ordering guide .......................................................... 19 7/08rev. 0 to rev. a deleted adp120-1.............................................................. universal changes to general description .................................................... 1 changes to dropout voltage parameter, table 1 .......................... 3 changes to thermal data section .................................................. 5 changes to figure 12 and figure 14 ............................................... 8 changes to figure 22 ........................................................................ 9 changes to table 6 and table 7 ..................................................... 14 changes to figure 46 and figure 47 captions ............................ 17 changes to ordering guide .......................................................... 18 6/08revision 0: initial version
adp120 rev. b | page 3 of 20 specifications v in = (v out + 0.4 v) or 2.3 v, whichever is greater; en = v in , i out = 10 ma, c in = c out = 1 f, t a = 25c, unless otherwise noted. table 1. parameter symbol conditions min typ max unit input voltage range v in t j = ?40c to +125c 2.3 5.5 v operating supply current i gnd i out = 0 a 11 a i out = 0 a, t j = ?40c to +125c 21 a i out = 10 ma 15 a i out = 10 ma, t j = ?40c to +125c 29 a i out = 100 ma 22 a i out = 100 ma, t j = ?40c to +125c 35 a shutdown current i gnd-sd en = gnd 0.1 a en = gnd, t j = ?40c to +125c 1.5 a fixed output voltage accuracy v out i out = 10 ma ?1 +1 % 100 a < i out < 100 ma, v in = (v out + 0.4 v) to 5.5 v ?2 +2 % 100 a < i out < 100 ma, v in = (v out + 0.4 v) to 5.5 v, t j = ?40c to +125c ?2.5 +2.5 % regulation line regulation ?v out /?v in v in = (v out + 0.4 v) to 5.5 v, i out = 1 ma, t j = ?40c to +125c ?0.03 +0.03 %/ v load regulation 1 ?v out /?i out i out = 1 ma to 100 ma 0.001 %/ma i out = 1 ma to 100 ma, t j = ?40c to +125c 0.005 %/ma dropout voltage 2 v dropout v out = 3.3 v tsot i out = 10 ma 8 mv i out = 10 ma, t j = ?40c to +125c 12 mv i out = 100 ma 80 mv i out = 100 ma, t j = ?40c to +125c 120 mv wlcsp i out = 10 ma 6 mv i out = 10 ma, t j = ?40c to +125c 9 mv i out = 100 ma 60 mv i out = 100 ma, t j = ?40c to +125c 90 mv start-up time 3 t start-up v out = 3.3 v 120 s current limit threshold 4 i limit 110 180 350 ma thermal shutdown thermal shutdown threshold ts sd t j rising 150 c thermal shutdown hysteresis ts sd-hys 15 c en input en input logic high v ih 2.3 v v in 5.5 v 1.2 v en input logic low v il 2.3 v v in 5.5 v 0.4 v en input leakage current v i-leakage en = v in or gnd 0.05 a en = v in or gnd, t j = ?40c to +125c 1 a undervoltage lockout uvlo input voltage rising uvlo rise t j = ?40c to +125c 2.25 v input voltage falling uvlo fall t j = ?40c to +125c 1.5 v hysteresis uvlo hys 120 mv output noise out noise 10 hz to 100 khz, v in = 5 v, v out = 3.3 v 65 v rms 10 hz to 100 khz, v in = 5 v, v out = 2.5 v 52 v rms 10 hz to 100 khz, v in = 5 v, v out = 1.2 v 40 v rms
adp120 rev. b | page 4 of 20 parameter symbol conditions min typ max unit power supply rejection ratio psrr 10 khz, v in = 5 v, v out = 3.3 v 60 db 10 khz, v in = 5 v, v out = 2.5 v 66 db 10 khz, v in = 5 v, v out = 1.2 v 70 db 1 based on an en dpoint calculation using 1 ma and 100 ma loads. see figure 6 for typical load regulation performance for loads l ess than 1 ma. 2 dropout voltage is defined as the input-to-output voltage differe ntial when the input voltage is set to the nominal output vol tage. this applies only for output voltages above 2.3 v. 3 start-up time is defined as the time between the rising edge of en to v out being at 90% of its nominal value. 4 current limit threshold is defi ned as the current at which the output voltage dr ops to 90% of the specif ied typical value. for example, the current limit for a 3.0 v output voltage is defined as the curre nt that causes the output voltage to drop to 90% of 3.0 v, or 2.7 v. recommended specifications: input and output capacitors table 2. parameter symbol conditions min typ max unit minimum input and output capacitance 1 c min t a = ?40c to +125c 0.70 f capacitor esr r esr t a = ?40c to +125c 0.001 1 1 the minimum input and output capacitance should be greater than 0.70 f over the full range of operating conditions. the full range of operating conditions in the application must be considered during devi ce selection to ensure that the minimum capa citance specification is met. x7r- and x5 r-type capacitors are recommended, y5v and z5u capacitors are not recommended for use with any ldo.
adp120 rev. b | page 5 of 20 absolute maximum ratings table 3. parameter rating vin to gnd ?0.3 v to +6 v vout to gnd ?0.3 v to vin en to gnd ?0.3 v to +6 v storage temperature range ?65c to +150c operating junction temperature range ?40c to +125c soldering conditions jedec j-std-020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal data absolute maximum ratings apply individually only, not in combination. the adp120 can be damaged when the junction temperature limits are exceeded. monitoring ambient temperature does not guarantee that t j is within the specified temperature limits. in applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. in applications with moderate power dissipation and low pcb thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. the junction temperature (t j ) of the device is dependent on the ambient temperature (t a ), the power dissipation of the device (p d ), and the junction-to-ambient thermal resistance of the package ( ja ). maximum junction temperature (t j ) is calculated from the ambient temperature (t a ) and power dissipation (p d ) using the formula t j = t a + ( p d ja ) junction-to-ambient thermal resistance ( ja ) of the package is based on modeling and calculation using a four-layer board. the junction-to-ambient thermal resistance is highly dependent on the application and board layout. in applications where high maximum power dissipation exists, close attention to thermal board design is required. the value of ja may vary, depending on pcb material, layout, and environmental conditions. the speci- fied values of ja are based on a four-layer, 4 3 pcb. refer to jesd 51-7 and jesd 51-9 for detailed information regarding board construction. for additional information, see application note an-617, microcsp tm wafer level chip s cale package . jb is the junction-to-board thermal characterization parameter with units of c/w. jb of the package is based on modeling and calculation using a four-layer board. jesd51-12, guidelines for reporting and using package thermal information , states that thermal characterization parameters are not the same as ther- mal resistances. jb measures the component power flowing through multiple thermal paths rather than a single path as in thermal resistance, jb . therefore, jb thermal paths include convection from the top of the package as well as radiation from the package, factors that make jb more useful in real- world applications. maximum junction temperature (t j ) is calculated from the board temperature (t b ) and power dissipation (p d ) using the following formula: t j = t b + ( p d jb ) refer to jesd51-8, jesd51-9, and jesd51-12 for more detailed information about jb . thermal resistance ja and jb are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 4. thermal resistance package type ja jb unit 5-lead tsot 170 43 c/w 4-ball, 0.4 mm pitch wlcsp 260 58 c/w esd caution
adp120 rev. b | page 6 of 20 pin configurations and function descriptions top view vin gnd (not to scale) nc = no connect en 5 vout 4 nc 1 2 3 07589-033 figure 3. 5-lead tsot pin configuration vin vout 12 en b a gnd 07589-03 top view (not to scale) 4 figure 4. 4-ball wlcsp pin configuration table 5. pin function descriptions pin no. mnemonic description tsot wlcsp 1 a1 vin regulator input supply. bypass vin to gnd with a 1 f or greater capacitor. 2 b2 gnd ground. 3 b1 en enable input. drive en high to turn on the regulator; drive en low to turn off the regulator. for automatic startup, connect en to vin. 4 n/a nc no connect. not connected internally. 5 a2 vout regulated output voltage. bypass vout to gnd with a 1 f or greater capacitor.
adp120 rev. b | page 7 of 20 typical performance characteristics v in = 2.3 v, v out = 1.8 v, i out = 10 ma, c in = c out = 1 f, t a = 25c, unless otherwise noted. 1.804 1.790 1.792 1.794 1.796 1.798 1.800 1.802 v out (v) t j (c) ?40c ?5c 25c 85c 125c i load = 10a i load = 100a i load = 1ma i load = 10ma i load = 100ma 07589-005 figure 5. output voltage vs. junction temperature 1.805 1.795 1.797 1.799 1.801 0.01 0.1 1 10 100 1.803 v out (v) i load (ma) 07589-006 figure 6. output volt age vs. load current 1.805 1.795 1.797 1.799 1.801 1.803 v out (v) v in (v) i load = 10a i load = 100a i load = 1ma i load = 10ma i load = 100ma 2.3 5.5 5.3 4.9 4.5 4.1 3.7 3.1 3.3 2.7 5.1 4.7 4.3 3.9 3.5 2.9 2.5 07589-007 figure 7. output voltage vs. input voltage 35 30 25 20 15 10 5 0 ground current (a) t j (c) ?40c ?5c 25c 85c 125c i load = 10a i load = 100a i load = 1ma i load = 10ma i load = 100ma 07589-008 figure 8. ground current vs. junction temperature 30 0 5 10 15 20 25 0.01 0.1 1 10 100 ground current (a) i load (ma) 07589-009 figure 9. ground current vs. load current 30 25 20 15 10 5 0 ground current (a) v in (v) i load = 10a i load = 100a i load = 1ma i load = 10ma i load = 100ma 2.3 5.5 5.3 4.9 4.5 4.1 3.7 3.1 3.3 2.7 5.1 4.7 4.3 3.9 3.5 2.9 2.5 07589-010 figure 10. ground current vs. input voltage
adp120 rev. b | page 8 of 20 0.35 0 0.05 0.10 ?50 ?25 0 25 50 75 100 125 0.15 0.20 0.25 0.30 shutdown current (a) temperature (c) v in = 2.30v v in = 2.50v v in = 3.00v v in = 3.50v v in = 4.20v v in = 5.50v 07589-011 figure 11. shutdown current vs. temperature at various input voltages 120 80 100 60 40 20 0 1 10 100 dropout voltage (mv) i load (ma) t a = 25c v out = 2.5v v out = 3.3v 07589-012 figure 12. dropout voltage vs. load current, tsot, v out = 2.5 v and 3.3 v 3.35 3.30 3.25 3.20 3.15 3.10 3.05 3.20 3.40 3.35 3.30 3.25 3.60 3.55 3.50 3.45 v out (v) v in (v) v out @ 1ma v out @ 10ma v out @ 20ma v out @ 50ma v out @ 100ma 07589-013 figure 13. output voltage vs. input voltage (in dropout), tsot, v out = 3.3 v 90 80 70 60 50 40 30 20 10 0 1 10 100 dropout voltage (mv) i load (ma) t a = 25c v out = 2.5v v out = 3.3v 07589-014 figure 14. dropout voltage vs. load current, wlcsp, v out = 2.5 v and 3.3 v 3.35 3.30 3.25 3.20 3.15 3.10 3.05 3.20 3.40 3.35 3.30 3.25 3.60 3.55 3.50 3.45 v out (v) v in (v) v out @ 1ma v out @ 10ma v out @ 20ma v out @ 50ma v out @ 100ma 07589-015 figure 15. output voltage vs. input voltage (in dropout), wlcsp, v out = 3.3 v 60 50 40 30 20 10 0 3.20 3.40 3.35 3.30 3.25 3.60 3.55 3.50 3.45 ground current (a) v in (v) i load @ 1ma i load @ 10ma i load @ 20ma i load @ 50ma i load @ 100ma 07589-016 figure 16. ground current vs. input voltage (in dropout)
adp120 rev. b | page 9 of 20 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100k 10k 1k 100 10m 1m psrr (db) frequency (hz) 100ma v ripple = 50mv v in = 5v v out = 1.2v c out = 1f 10ma 1ma 100a no load 07589-017 figure 17. power supply reje ction ratio vs. frequency 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100k 10k 1k 100 10m 1m psrr (db) frequency (hz) 100ma v ripple = 50mv v in = 5v v out = 1.8v c out = 1f 10ma 1ma 100a no load 07589-018 figure 18. power supply reje ction ratio vs. frequency 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100k 10k 1k 100 10m 1m psrr (db) frequency (hz) 100ma v ripple = 50mv v in = 5v v out = 3.3v c out = 1f 10ma 1ma 100a no load 07589-019 figure 19. power supply reje ction ratio vs. frequency 0 ?20 ?40 ?60 ?80 ?100 ?120 10 100k 10k 1k 100 10m 1m psrr (db) frequency (hz) 3.3v/100ma 3.3v/100a 1.2v/100ma 1.2v/100a 1.8v/100ma 1.8v/100a 07589-020 figure 20. power supply reje ction ratio vs. frequency, various output voltages and load currents 10 0.01 0.1 1 10 10k 1k 100 100k noise (v/ hz) frequency (hz) v out = 1.2v v out = 1.8v v out = 3.3v 07589-021 figure 21. output noise spectrum, v in = 5 v, i load = 10 ma, c out = 1 f 70 60 50 40 30 20 10 0 0.001 0.01 0.1 1 10 100 noise (v rms) i load (ma) v out =3.3v v out =2.5v v out = 1.8v v out = 1.5v v out =1.2v 07589-022 figure 22. output noise vs. lo ad current and output voltage v in = 5 v, c out = 1 f
adp120 rev. b | page 10 of 20 (40s/div) (100ma/div) (50mv/div) i load v out v in = 5v v out = 1.8v 1ma to 100ma load step, 2.5a/s 07589-023 figure 23. load transient response, c in and c out = 1 f (40s/div) (100ma/div) (50mv/div) i load v out v in = 5v v out = 1.8v 1ma to 100ma load step, 2.5a/s 07589-024 figure 24. load transient response, c in and c out = 4.7 f (4s/div) (1v/div) (10mv/div) v in v out v out = 1.8v, c in = c out = 1f 4v to 5v input voltage step, 2v/s 07589-125 figure 25. line transient resp onse, load current = 100 ma (10s/div) (1v/div) (10mv/div) v in v out v out = 1.8v, c in = c out = 1f 4v to 5v input voltage step, 2v/s 07589-026 figure 26. line transient re sponse, load current = 1 ma
adp120 rev. b | page 11 of 20 theory of operation the adp120 is a low quiescent current, low dropout linear regulator that operates from 2.3 v to 5.5 v and provides up to 100 ma of output current. drawing a low 22 a of quies- cent current (typical) at full load makes the adp120 ideal for battery-operated portable equipment. shutdown current consumption is typically 100 na. optimized for use with small 1 f ceramic capacitors, the adp120 provides excellent transient performance. vin vout r1 r2 gnd en short circuit, uvlo, and thermal protect 0.8v reference shutdown 0 7589-127 figure 27. internal block diagram internally, the adp120 consists of a reference, an error amplifier, a feedback voltage divider, and a pmos pass transistor. output current is delivered via the pmos pass device, which is controlled by the error amplifier. the error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. if the feedback voltage is lower than the reference voltage, the gate of the pmos device is pulled lower, allowing more current to pass and increasing the output voltage. if the feedback voltage is higher than the reference voltage, the gate of the pmos device is pulled higher, allowing less current to pass and decreasing the output voltage. the adp120 is available in output voltages ranging from 1.2 v to 3.3 v. the adp120 uses the en pin to enable and disable the vout pin under normal operating conditions. when en is high, vout turns on; when en is low, vout turns off. for automatic startup, en can be tied to vin.
adp120 rev. b | page 12 of 20 applications information capacitor selection output capacitor the adp120 is designed for operation with small, space-saving ceramic capacitors, but functions with most commonly used capacitors as long as care is taken with regard to the effective series resistance (esr) value. the esr of the output capacitor affects stability of the ldo control loop. a minimum of 0.70 f capacitance with an esr of 1 or less is recommended to ensure stability of the adp120. transient response to changes in load current is also affected by output capacitance. using a larger value of output capacitance improves the transient response of the adp120 to large changes in load current. figure 28 and figure 29 show the transient responses for output capacitance values of 1 f and 4.7 f, respectively. (400ns/div) (100ma/div) (50mv/div) i load v out v out = 1.8v, c in = c out = 1f 1ma to 100ma load step, 2.5a/s 07589-128 figure 28. output transient response, c out = 1 f (400ns/div) (100ma/div) (50mv/div) i load v out v out = 1.8v, c in = c out = 4.7f 1ma to 100ma load step, 2.5a/s 07589-129 figure 29. output transient response, c out = 4.7 f input bypass capacitor connecting a 1 f capacitor from vin to gnd reduces the cir- cuit sensitivity to pcb layout, especially when long input traces or high source impedance are encountered. if greater than 1 f of output capacitance is required, increase the input capacitor to match it. input and output capacitor properties use any good quality ceramic capacitors with the adp120, as long as they meet the minimum capacitance and maximum esr requirements. ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary tempera- ture range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v or 10 v are recommended for best performance. y5v and z5u dielectrics are not recommended for use with any ldo because of their poor temperature and dc bias characteristics. figure 30 depicts the capacitance vs. voltage bias characteristic of a 0402 1 f, 10 v, x5r capacitor. the voltage stability of a capa- citor is strongly influenced by the capacitor size and voltage rating. in general, a capacitor in a larger package or higher voltage rating exhibits better stability. the temperature variation of the x5r dielectric is about 15% over the ?40c to +85c temperature range and is not a function of package or voltage rating. 1.2 1.0 0.8 0.6 0.4 0.2 0 024681 voltage (v) capacitance (f) 0 murata part number: grm155r61a105ke15 07589-126 figure 30. capacitance vs. voltage characteristic use equation 1 to determine the worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage. c eff = c bias (1 ? tempco ) (1 ? tol) (1) where: c bias is the effective capacitance at the operating voltage. tempco is the worst-case capacitor temperature coefficient. tol is the worst-case component tolerance. in this example, tempco over ?40c to +85c is assumed to be 15% for an x5r dielectric. tol is assumed to be 10%, and c bias is 0.94 f at 1.8 v, as shown in figure 30 . substituting these values in equation 1 yields c eff = 0.94 f (1 ? 0.15) (1 ? 0.1) = 0.719 f
adp120 rev. b | page 13 of 20 therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the ldo over temper- ature and tolerance at the chosen output voltage. to guarantee the performance of the adp120, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. undervoltage lockout the adp120 has an internal undervoltage lockout circuit that disables all inputs and the output when the input voltage is less than approximately 2.2 v. this ensures that the inputs and the output of the adp120 behave in a predictable manner during power-up. enable feature the adp120 uses the en pin to enable and disable the vout pin under normal operating conditions. figure 31 shows a rising voltage on en crossing the active threshold, and vout turns on. when a falling voltage on en crosses the inactive threshold, vout turns off. (40ms/div) (500mv/div) v in = 5v v out = 1.8v c in = c out = 1f i load = 100ma en v out 07589-124 figure 31. typical en pin operation as shown in figure 31 , the en pin has hysteresis built-in. this prevents on/off oscillations that can occur due to noise on the en pin as it passes through the threshold points. the en pin active/inactive thresholds are derived from the vin voltage; therefore, these thresholds vary with changing input voltage. figure 32 shows typical en active/inactive thresholds when the input voltage varies from 2.3 v to 5.5 v. 1.10 1.05 1.00 0.95 0.90 0.85 0.80 0.75 0.70 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 5.50 typical en thresholds (v) v in (v) en active en inactive 07589-025 figure 32. typical en pin thresholds vs. input voltage the adp120 utilizes an internal soft start to limit the inrush current when the output is enabled. the start-up time for the 1.8 v option is approximately 120 s from the time the en active threshold is crossed to when the output reaches 90% of its final value. the start-up time is somewhat dependent on the output voltage setting and increases slightly as the output voltage increases. 6 0 1 2 3 4 5 02 180 160 14012010080 60 4020 volts (v) time (s) en 3.3v 1.8v 1.2v 07589-133 0 0 figure 33. typical start-up time
adp120 rev. b | page 14 of 20 current-limit and thermal overload protection the adp120 is protected against damage due to excessive power dissipation by current and thermal overload protection circuits. the adp120 is designed to current limit when the output load reaches 150 ma (typical). when the output load exceeds 150 ma, the output voltage reduces to maintain a constant current limit. thermal overload protection is built-in, limiting the junction temperature to a maximum of 150c (typical). under extreme conditions (that is, high ambient temperature and power dissi- pation) when the junction temperature starts to rise above 150c, the output turns off, reducing the output current to zero. when the junction temperature drops below 135c, the output turns on again thereby restoring output current to its nominal value. consider the case where a hard short from vout to gnd occurs. at first, the adp120 current limits, conducting only 150 ma into the short. if self-heating of the junction is great enough to cause its temperature to rise above 150c, thermal shutdown activates, turning off the output and reducing the output current to zero. as the junction temperature cools and drops below 135c, the output turns on and conducts 150 ma into the short, again causing the junction temperature to rise above 150c. this thermal oscillation between 135c and 150c causes a current oscillation between 150 ma and 0 ma that continues as long as the short remains at the output. current- and thermal-limit protections are intended to protect the device against accidental overload conditions. for reliable operation, device power dissipation must be externally limited to prevent junction temperatures from exceeding 125c. thermal considerations in most applications, the adp120 does not dissipate much heat due to its high efficiency. however, in applications with high ambient temperature and high supply voltage-to-output voltage differential, the heat dissipated in the package is large enough to cause the junction temperature of the die to exceed the maximum junction temperature of 125c. when the junction temperature exceeds 150c, the converter enters thermal shutdown. it recovers only after the junction temperature has decreased below 135c to prevent any permanent damage. therefore, thermal analysis for the chosen application is very important to guarantee reliable performance over all conditions. the junction temperature of the die is the sum of the ambient temperature of the environment and the tempera- ture rise of the package due to the power dissipation, as shown in equation 2. to guarantee reliable operation, the junction temperature of the adp120 must not exceed 125c. to ensure the junction temperature stays below this maximum value, the user needs to be aware of the parameters that contribute to junction temperature changes. these parameters include ambient temper- ature, power dissipation in the power device, and thermal resistances between the junction and ambient air ( ja ). the ja number is dependent on the package assembly compounds that are used and the amount of copper used to solder the package gnd pins to the pcb. table 6 shows typical ja values of the 5-lead tsot and 4-ball wlcsp packages for various pcb copper sizes. table 7 shows the typical jb value of the 5-lead tsot and 4-ball wlcsp. table 6. typical ja values copper size (mm 2 ) tsot (c/w) wlcsp (c/w) 0 1 170 260 50 152 159 100 146 157 300 134 153 500 131 151 1 device soldered to minimum size pin traces. table 7. typical jb values tsot (c/w) wlcsp (c/w) 42.8 58.4 the junction temperature of the adp120 can be calculated from the following equation: t j = t a + ( p d ja ) (2) where: t a is the ambient temperature. p d is the power dissipation in the die, given by p d = [(v in ? v out ) i load ] + ( v in i gnd ) (3) where: i load is the load current. i gnd is the ground current. v in and v out are input and output voltages, respectively. power dissipation due to ground current is quite small and can be ignored. therefore, the junction temperature equation simplifies to the following: t j = t a + {[( v in ? v out ) i load ] ja } (4) as shown in equation 4, for a given ambient temperature, input- to-output voltage differential, and continuous load current, there exists a minimum copper size requirement for the pcb to ensure the junction temperature does not rise above 125c. figure 34 to figure 47 show junction temperature calculations for different ambient temperatures, load currents, v in -to-v out differentials, and areas of pcb copper.
adp120 rev. b | page 15 of 20 140 120 100 80 60 40 20 0 0.5 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 junction temperature, t j (c) v in ? v out (v) max junction temperature i load = 1ma i load = 10ma i load = 25ma i load = 50ma i load = 75ma i load = 100ma 07589-134 figure 34. tsot, 500 mm 2 of pcb copper, t a = 25c 140 120 100 80 60 40 20 0 0.5 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 junction temperature, t j (c) v in ? v out (v) max junction temperature i load = 1ma i load = 10ma i load = 25ma i load = 50ma i load = 75ma i load = 100ma 07589-027 figure 35. tsot, 100 mm 2 of pcb copper, t a = 25c 140 120 100 80 60 40 20 0 0.5 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 junction temperature, t j (c) v in ? v out (v) max junction temperature i load = 1ma i load = 10ma i load = 25ma i load = 50ma i load = 75ma i load = 100ma 07589-028 figure 36. tsot, 0 mm 2 of pcb copper, t a = 25c 140 120 100 80 60 40 20 0 0.5 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 junction temperature, t j (c) v in ? v out (v) max junction temperature i load = 1ma i load = 10ma i load = 100ma 07589-137 i load = 25ma i load = 50ma i load = 75ma figure 37. tsot, 500 mm 2 of pcb copper, t a = 50c 140 120 100 80 60 40 20 0 0.5 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 junction temperature, t j (c) v in ? v out (v) max junction temperature 07589-030 i load = 1ma i load = 10ma i load = 100ma i load = 25ma i load = 50ma i load = 75ma figure 38. tsot, 100 mm 2 of pcb copper, t a = 50c 140 120 100 80 60 40 20 0 0.5 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 junction temperature, t j (c) v in ? v out (v) max junction temperature 07589-031 i load = 1ma i load = 10ma i load = 100ma i load = 25ma i load = 50ma i load = 75ma figure 39. tsot, 0 mm 2 of pcb copper, t a = 50c
adp120 rev. b | page 16 of 20 140 120 100 80 60 40 20 0 0.5 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 junction temperature, t j (c) v in ? v out (v) max junction temperature i load = 100ma 07589-140 i load = 1ma i load = 10ma i load = 25ma i load = 50ma i load = 75ma figure 40. wlcsp, 500 mm 2 of pcb copper, t a = 25c 140 120 100 80 60 40 20 0 0.5 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 junction temperature, t j (c) v in ? v out (v) max junction temperature 07589-141 i load = 1ma i load = 10ma i load = 25ma i load = 50ma i load = 75ma i load = 100ma figure 41. wlcsp, 100 mm 2 of pcb copper, t a = 25c 140 120 100 80 60 40 20 0 0.5 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 junction temperature, t j (c) v in ? v out (v) max junction temperature 07589-142 i load = 1ma i load = 10ma i load = 100ma i load = 25ma i load = 50ma i load = 75ma figure 42. wlcsp, 0 mm 2 of pcb copper, t a = 25c 140 120 100 80 60 40 20 0 0.5 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 junction temperature, t j (c) v in ? v out (v) max junction temperature 07589-143 i load = 1ma i load = 10ma i load = 100ma i load = 25ma i load = 50ma i load = 75ma figure 43. wlcsp, 500 mm 2 of pcb copper, t a = 50c 140 120 100 80 60 40 20 0 0.5 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 junction temperature, t j (c) v in ? v out (v) max junction temperature 07589-144 i load = 1ma i load = 10ma i load = 100ma i load = 50ma i load = 75ma i load = 25ma figure 44. wlcsp, 100 mm 2 of pcb copper, t a = 50c 140 120 100 80 60 40 20 0 0.5 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 junction temperature, t j (c) v in ? v out (v) max junction temperature 07589-145 i load = 1ma i load = 10ma i load = 100ma i load = 25ma i load = 50ma i load = 75ma figure 45. wlcsp, 0 mm 2 of pcb copper, t a = 50c
adp120 rev. b | page 17 of 20 in cases where the board temperature is known, use the thermal characterization parameter, jb , to estimate the junction tem- perature rise. maximum junction temperature (t j ) is calculated from the board temperature (t b ) and power dissipation (p d ) using the formula t j = t b + ( p d jb ) (5) j1 analog devices adp120-xx-evalz vin vout gnd en gnd c1 c2 gnd gnd u1 07589-032 140 120 100 80 60 40 20 0 0.5 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 junction temperature, t j (c) v in ? v out (v) max junction temperature 07589-146 i load = 1ma i load = 10ma i load = 100ma i load = 50ma i load = 75ma i load = 25ma figure 48. tsot pcb layout 07589-148 figure 46. tsot, t b = 85c 140 120 100 80 60 40 20 0 0.5 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 junction temperature, t j (c) v in ? v out (v) max junction temperature 07589-147 i load = 1ma i load = 10ma i load = 100ma i load = 50ma i load = 75ma i load = 25ma figure 49. wlcsp pcb layouttop side 07589-149 figure 47. wlcsp, t b = 85c pcb layout considerations improve heat dissipation from the package by increasing the amount of copper attached to the pins of the adp120. however, as listed in table 6 , a point of diminishing return is eventually reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. place the input capacitor as close as possible to the vin and gnd pins. place the output capacitor as close as possible to the vout and gnd pins. use of 0402- or 0603-size capacitors and resistors achieves the smallest possible footprint solution on boards where area is limited. figure 50. wlcsp pcb layoutbottom side
adp120 rev. b | page 18 of 20 outline dimensions 100708-a * compliant to jedec standards mo-193-ab with the exception of package height and thickness. 1.60 bsc 2.80 bsc 1.90 bsc 0.95 bsc 0.20 0.08 0.60 0.45 0.30 8 4 0 0.50 0.30 0.10 max * 1.00 max * 0.90 max 0.70 min 2.90 bsc 54 12 3 seating plane figure 51. 5-lead thin small outline transistor package [tsot] (uj-5) dimensions shown in millimeters 101507-a 0.050 nom coplanarity 0.860 0.820 sq 0.780 0.230 0.200 0.170 0.280 0.260 0.240 0.660 0.600 0.540 bottom view (ball side up) top view (ball side down) a 12 b a1 ball corner seating plane 0.40 ball pitch figure 52. 4-ball wafer level chip scale package [wlcsp] (cb-4-2) dimensions shown in millimeters
adp120 rev. b | page 19 of 20 ordering guide model 1 temperature range output voltage (v) 2 package description package option branding adp120-aujz12r7 3 C40c to +125c 1.2 5-lead tsot uj-5 l9r adp120-aujz15r7 3 C40c to +125c 1.5 5-lead tsot uj-5 l9q adp120-aujz18r7 3 C40c to +125c 1.8 5-lead tsot uj-5 l9p adp120-aujz33r7 3 C40c to +125c 3.3 5-lead tsot uj-5 l9n adp120-acbz12r7 3 C40c to +125c 1.2 4-ball wlcsp cb-4-2 lbj ADP120-ACBZ15R7 3 C40c to +125c 1.5 4-ball wlcsp cb-4-2 lbk adp120-acbz25r7 3 C40c to +125c 2.5 4-ball wlcsp cb-4-2 lbu adp120-acbz28r7 3 C40c to +125c 2.8 4-ball wlcsp cb-4-2 lbw adp120-acbz30r7 3 C40c to +125c 3.0 4-ball wlcsp cb-4-2 lby adp120-18-evalz 3 1.8 adp120 1.8 v output evaluation board adp120-15-evalz 3 1.5 adp120 1.5 v output evaluation board adp120-12-evalz 3 1.2 adp120 1.2 v output evaluation board adp120cb-2.8-evalz 3 2.8 adp120 wlcsp 2.8 v output evaluation board adp120cb-2.5-evalz 3 2.5 adp120 wlcsp 2.5 v output evaluation board adp120cb-1.8-evalz 3 1.8 adp120 wlcsp 1.8 v output evaluation board adp120cb-1.5-evalz 3 1.5 adp120 wlcsp 1.5 v output evaluation board adp120cb-1.2-evalz 3 1.2 adp120 wlcsp 1.2 v output evaluation board adp120-bl1-evz 3 blank evaluation board 1 for new designs, see the adp121 . 2 for additional voltage options, contac t your local analog devices, inc., sales or distribution representative . 3 z = rohs compliant part.
adp120 rev. b | page 20 of 20 notes ?2008C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07589-0-4/09(b)

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